1. Field of the Invention
The present invention relates to spread spectrum communication systems using PN coding techniques and, more particularly, to generating data clocks synchronous with PN code epochs.
2. Prior Art
Spread spectrum (SS) systems, which may be CDMA systems, are well known in the art. SS systems can employ a transmission technique in which a pseudo-noise (PN) PN-code is used as a modulating waveform to spread the signal energy over a bandwidth much greater than the signal information bandwidth. At the receiver, the signal is de-spread using a synchronized replica of the PN-code.
In general, there are two basic types of SS systems: direct sequence spread spectrum systems (DSSS) and frequency hop spread spectrum systems (FHSS).
The DSSS systems spread the signal over a bandwidth fRF±Rc, where fRF represents the carrier frequency and Rc represents the PN-code chip rate, which in turn may be an integer multiple of the symbol rate Rs. Multiple access systems employ DSSS techniques when transmitting multiple channels over the same frequency bandwidth to multiple receivers, each receiver sharing a common PN code or having its own designated PN-code. Although each receiver receives the entire frequency bandwidth, only the signal with the receiver's matching PN-code will appear intelligible; the rest appears as noise that is easily filtered. These systems are well known in the art and will not be discussed further.
FHSS systems employ a PN-code sequence generated at the modulator that is used in conjunction with an m-ary frequency shift keying (FSK) modulation to shift the carrier frequency fRF at a hopping rate Rh. A FHSS system divides the available bandwidth into N channels and hops between these channels according to the PN-code sequence. At each frequency hop time, a PN generator feeds a frequency synthesizer a sequence of n chips that dictates one of 2n frequency positions. The receiver follows the same frequency hop pattern. FHSS systems are also well known in the art and need not be discussed further.
As noted, the DSSS system PN-code sequence spreads the data signal over the available bandwidth such that the signal appears to be noise-like and random; but the signal is deterministic to a receiver applying the same PN-code to de-spread the signal. However, the receiver must also apply the same PN-code at the appropriate phase in order to de-spread the incoming signal, which explicitly implies synchronization between the receiver and transmitter.
In addition, the receiver data clock used by the receiver must be the same as the data clock used by the transmitter in order to retrieve user data. Generally, the transmitter data clock rate is generated at an octave rate such as 2n, n=0,1,2,3 . . . It will be appreciated that as n increases, the step between clock rates also increases exponentially as 2(n+1)−2n=2n. Moreover, the power and bandwidth requirements are also increased proportionally for each step. For example, a system operating with a data clock at 22 data clock cycles might require 10 watts; a similar system would require 20 watts when operating at 23 data clock cycles.
In addition, to retrieve the PN encoded data the receiver must complete two generally independent steps: first it must synchronize with the PN code, and then obtain the data clock from a bit/symbol synchronizer such as a narrow band phase lock loop tracking filter and associated circuitry. The multiple steps and hardware add both time and expense to the receiver performance parameters.
It is therefore desirable to provide a method and system whereby the data clock and component PN codes are related in order to reduce the receiver steps and hardware. It is also desirable that the method and system allow for a selection of data clock rates with other than exponential growth rates.